Model NO.V-300
32-bit PCI local bus standard Revision 2.1 compliant
133 MHz zero wait-state memory mapping I/O burst write
32-bit ROM address decoding for 32KB,64 KB size
Flash memory interface for VGA BIOS upgrade
RAMDAC snoop
AGP 2.0 compliant configuration setting
AGP 2X 266 MHz with maximum 32 stages pipeline full side-band function
Built-in a high performace 128-bit 3D engine
Built-in 32-bit floating point VLIW triangle setup engine
Built-in 8K bytes,texture cache -64KB,128KB,256KB and 512KB Turbo Queue size)
AGP 2X for command fetch,texture fetch and parsing
166 MHz 128-bit DRAM plus 125 MHz 3D engine clock
Flat,and Gouraud shading
Z-test,Alpha-test,and scissors clipping test
256 ROPs
MIPMAP with point-sampled,linear,bi-linear,and tri-linear texture filtering
Fogging,alpha blending
Supports Turbo Queue (Software Command Queue in off screen memory)
Built in Direct Draw Accelerator
Built-in an 1T 128-bit BITBLT graphics engine
Maxium 64 MB frame buffer with linear addressing
AGP 2X mode access for all 2D engine functions
SGRAM block write function for Bitblt command
Supports AGP 2X mode bus master code fetching
Direct DVD to TV playback
Single frame buffer architecture
Two independent video windows with overlay function and scaling factors
Supports YUV-to-RGB color space conversion
Supports bi-linear video interpolation with in-teger
Supports graphics and video overlay function
Independent graphics and video formats
Independent two video formats -16 color-key and /or chroma-key operations
Video only mode
Video CD or DVD to TV playback mode
Built-in video decoder interface
Supports input video capture and playback tear free auto flipping
Supports independent VBI capture
Supports DVD sub-picture playback overlay
Supports DVD playback auto-flipping
128-bit DRAM channel interface with maxi-mum 2.65 GB/s bandwidth
Supports up to 4 ranks of DRAM for DRAM interface
Up to 2-64 MB Memory configuration
Fully internal 128-bit display memory path
VGA BIOS auto memory size detecting
SGRAM block write operation
Virtual screen up to 4096x4096
Built-in programmable 24-bit true-color RAMDAC up to 350MHz pixel clock
Built-in three clock generators
Built-in standard feature connector logic support
Built-in VIP 1.1,VIP 2.0 video port interface
Built-in flash ROM programming interface
Built-in VESA Plug & Display for CH7003, PanelLink and LVDS digital interface
Inplemented by 0.25 um 1.8V CMOS technology with 3.3V/2.5V LVTTL tolerance I/O buffers
365-balls 27x27 mm BGA package