ALADDiN-P4 (桌面型)

ALADDiN-P4M (移动型)

Easy-to-Design Solution for building High-Performace Intel Pentium 4 Platforms

IntelPentium4 solution supporting DDR333 / SDR133 and Ultra ATA/133

The ALADDiN-P4 uses M1671 - ALi’s new generation PCI Northbridge chip for the latest IntelR PentiumR 4 Processor supporting 400MHz front side bus (FSB). It provides high-performance memory interface for both SDR 100/133 and DDR 200/266/333 DRAM. The latest DDR333 memory enables a 2.7 GB/sec peak bandwidth between the system memory and Northbridge to boost system performance to the next level.

Based from it's former DDR chipset family (ALADDiN-Pro 5 and ALiMAGiK 1), the ALADDiN-P4 offers the most minimum effort to design your IntelR PentiumR 4 based systems. This ensures greater stability and higher-compatibility, resulting to an overall decrease in design cost.

With Ultra ATA66/100/133 supported, the ALADDiN-P4 provides an enhanced data-rate transfer that is capable of supporting larger capacity and faster hard drives.

The M1671 seamlessly works with series of integrated Southbridge chipsets such as M1535, M1535D, M1535+ M1535D+, providing a complete, flexible and cost-effective solution for PC system designers

Processor Support

• Supports IntelR PentiumR 4 microprocessors. Host bus frequency can be up to 400MHz.
• 64-bit data bus and 32-bit addressing
• Optimum buffering architecture design for CPU to memory, AGP and PCI read/write
• Flexible configured to support back to back read transfer in 1QW or 2QW
• Supports back to back write transfer
• Supports synchronous / pseudo asynchronous clock mode between processor and memory interface with optimized latency

Memory Support

• Supports PC-100, PC-133, DDR200, DDR266, DDR333DRAM
• Supports symmetrical and asymmetrical SDR / DDR DRAM addressing
• Supports 64, 128, 256, 512Mbit SDR / DDR DRAM
• Maximum memory size: 3GB
• Supports 6 memory rows with per byte access on each row
• Supports memory shadowing
• X-1-1-1-1-1-1-1 back-to-back page hit
• CAS before RAS and self refresh for SDR DRAM
• Pipelined SDR / DDR DRAM cycle control with hidden pre-charge
• Dynamic switching CKE algorithm
• Supports LVTTL / SSTL2 signal level

Accelerated Graphics Port (AGP) Interface

• Supports AGP specification V2.0 with Fast Write (FW) supported
• Supports up to 128 entries table look aside buffer for Graphic Address Remapping Table(GART)
• AGP 66MHz protocol
• AGP 1X/2X/4X sideband function
• 28 entries Request queue
• 64 QWORDs Read buffer
• 32 QWORDs Write buffer

PCI Bus Support

• Supports synchronous / asynchronous clock mode between the processor bus and the PCI bus
• 32-bit Address / Data PCI bus using PCI bus driver technology
• Supports up to 7 PCI masters excluding the M1671 and PCI-to-ISA bridge
• Parity protection on all PCI bus signals
• Fully supports PCI Configuration Space Enable (CSE) protocol
• Fully compliant with PCI Rev. 2.2
• Supports delayed transaction
• Dynamic memory pre-fetch algorithm and programmable post write flush algorithm
• Data Collection/Write assembly of line bursts
• Supports concurrent PCI bus burst transfer at zero wait-states
• 133 MB/sec data streaming for PCI bus to SDR / DDR DRAM access with minimum latency

Power Management

• Supports ACPI 1.0b and Legacy green
• Supports AGP Mobile BUSY# / STOP#
• Internally dynamic clock stop

Packaging

• 629 balls 37.5x37.5mm BGA package