ALi M1672 Northbridge with Integrated Graphic Chip supporting Intel? Pentium? 4 Processor with DDR 266, SDR 133 and Ultra-ATA 133 for Mobile Platforms

M1672 is ALi and Trident's new generation of low-power PCI North bridge solution supporting the latest Intel? Pentium? 4 Processor family with DDR memory technology and fully PC2001 compliant. M1672 interfaces to the Pentium? 4 processor through the 400MHz P4 System Bus and supports high-performance PC2100 memory system consisted of 64-bit memory bus with either 100/133 SDR or 200/266 DDR memory chips. On the graphics side, M1672 integrates the DX7 and DX8 ready 2D/3D graphics core (CyberBlade XP?) from Trident Microsystems. The CyberBlade XP? graphics core contains Dual-Pixel Quad-Texture rendering pipelines plus a partial hardware Transform and Lighting (T&L) unit, and can provide enough processing power to satisfy demanding 3D graphics requirements. With Ultra ATA133 supported, the ALADDiN-P4 provides an enhanced data-rate transfer that is capable of supporting larger capacity and faster hard drives.

The M1672 seamlessly works with series of integrated South bridge chipsets such as M1535+ providing a complete, flexible and cost-effective solution for PC system designers.

Block Diagram

ALi PCI Northbridge Core Logic Processor Support

Supports Intel Pentium 4 microprocessor family with host bus frequency can be up to 400MHz

64-bit data bus and 32-bit addressing bus

Optimum buffering architecture design for CPU to memory,

AGP and PCI read/write

Flexible configuration to support back-to-back read transfer in 1QW or 2QW

Supports back-to-back write transfer

Supports synchronous / pseudo asynchronous clock mode between processor and memory interface with optimized latency

Memory Support

Supports SDR DRAM PC-100, PC-133

Supports DDR up to 200, 266MHz

Supports symmetrical and asymmetrical SDRAM /DDR addressing

Supports 64, 128, 256, 512Mbit SDRAM / DDR

Maximum memory size: 3GB

Supports 6 memory rows with per byte access on each row

Supports memory shadowing

X-1-1-1-1-1-1-1 back-to-back page hit

CAS before RAS and self refresh for SDRAM

Pipelined SDRAM / DDR cycle control with hidden pre-charge

Dynamic switching CKE algorithm

Supports LVTTL / SSTL2 signal level

Advanced Mobile Power Management

Low power cell design

Suspend and standby modes

Internal clock gating on each functional block

PCIPM (H/W PCI initiated)

AGP Busy#/Stop# and PCI Clock Run#

ACPI and DPMS support

High Performance DirectX 7.0 3D Engine DVD Playback

PCI Bus Support

Supports synchronous / asynchronous clock mode between the processor bus and the PCI bus

32-bit Address / Data PCI bus using PCI bus driver technology

Supports up to 5 PCI masters excluding the M1672 and PCI-to-ISA bridge

Parity protection on all PCI bus signals

Fully supports PCI Configuration Space Enable (CSE) protocol

Fully compliant with PCI Rev. 2.2

Supports delayed transaction

Dynamic memory prefetch algorithm and programmable post write flush algorithm

Data Collection/Write assembly of line bursts

Supports concurrent PCI bus burst transfer at zero wait-states

Trident CyberBlade XP? Graphic Core Highly Integrated Graphics Engine

Advanced CyberBlade XP? Dual-Pixel, Quad-Texture Single-Pass 3D rendering engine

128-bit internal bus interface to Core logic block

Supports Microsoft DirectX 7.0/8.0 with Cubic Mapping

Integrated Dual-channel LVDS transmitter

Digital interface to external TMDS transmitter

Digital interface to external TV encoder

DVD hardware assist with Motion Compensation (MC) and Inverse Discrete Cosine Transform (IDCT)

TrueVideo? with Advanced Video De-interlacing

PC2001 Compliant

Packaging

645 balls in 37.5 x 37.5mm BGA package