DDR SDRAM

64Mb DDR SDRAM

Data Sheet	Micron Parts
64Mb: x32 DDR SDRAM	MT46V2M32

128Mb DDR SDRAM

Data Sheet	Micron Parts
128Mb: x32 DDR SDRAM	MT46V4M32
128Mb: x4, x8, x16 DDR SDRAM	MT46V16M8 MT46V32M4 MT46V8M16

256Mb DDR SDRAM

Data Sheet	Micron Parts
256Mb: x4, x8, x16 DDR SDRAM	MT46V16M16 MT46V16M16D1 MT46V16M16D2 MT46V32M8 MT46V64M4

DDR SDRAM (Advance Information)

Data Sheet
256Mb: x4, x8, x16 DDR333 SDRAM Addendum	MT46V64M4 MT46V32M8 MT46V16M16
512Mb: x4, x8, x16 DDR SDRAM	MT46V128M4, MT46V64M8, MT46V32M16

64Mb: x32 DDR SDRAM

 Part Features

• Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Reduced output drive option
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, 8, or full page
• 32ms, 4,096-cycle auto refresh (7.8µs/cycle)
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Programmable I/O (SSTL_2 compatible) – reduced and impedance matched

128Mb: x32 DDR SDRAM

 Part Features

• VDD = +2.5V ±0.125V, VDDQ = +2.5V ±0.125V
• Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Reduced output drive option
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, 8, or full page
• 32ms, 4,096-cycle auto refresh
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 2.5V I/O (SSTL_2 compatible)
• DQS per byte on the FBGA package
• 1.8V VDDQ for FBGA package
• tRAS lockout

128Mb: x4, x8, x16 DDR SDRAM

Part Features

• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two – one per byte)
• x16 has programmable IOL/IOH option
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
  

Part Options

256Mb: x4, x8, x16 DDR SDRAM

Part Features

• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported

256Mb: x4, x8, x16 DDR333 SDRAM Addendum

Part Features

• 167 MHz Clock, 333 MHz data rate
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte)
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two - one per byte)
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
• 2.5V I/O (SSTL_2 compatible)
• tRAS lockout ( tRAP = tRCD)
• Backwards compatible with DDR200 and DDR266

512Mb: x4, x8, x16 DDR SDRAM

Part Features

• •VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• x16 has programmable IOL/IOV.
• Concurrent auto precharge option is supported
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)