256Mb/288Mb:16 Meg x 16/18 RDRAM

Part Features

• High-speed 300 MHz, 356 MHz, and 400 MHz clocks with 2x data rates
• 1.6 GB/s peak I/O bandwidth
• Rambus ® signaling level (RSL) using differential 300 MHz, 356 MHz, and 400 MHz transmit and receive clocks
• Packet-oriented Rambus protocol transmitted in 8-bit-long packets
• Separate control (8-bit) and data (18-bit) buses for increased data bandwidth capability
• Control bus with separate row (3-bit) and column (5-bit) buses for easier command scheduling
• Programmable output delay timing for roundtrip delay of one to five cycles
• Support for up to four simultaneous transactions (within bank restrictions)
• Write buffer to reduce READ latency
• Three precharge mechanisms for controller flexibility
• Programmable power states for flexibility in power consumption versus data access time
• Power-down Self-Refresh and Active Refresh
• Organization: 2KB pages and 32 banks, x16 or x18
• FBGA package
• Interleaved Data Mode (IDM) on the MT6V16M18 for system level error correction
• 32ms, 16,384 cycle refresh
• 2.5V power supply with 1.8V CMOS supply for I/Os

Part Number Example:MT6V16M16F2-3B