chipset key features

SiS740 Integrated DDR Solution for AMD? Platform

Host Interface Controller

- Support AMD Athlon? /Duro?n CPUs

- 266MHz Front-Side Bus

Integrated DDR SDRAM Controller

- Up to 3 DIMMs of DDR266/PC133

- Maximum 1.5GB System Memory

- Suspend-to-RAM (STR)

Integrated Real256? 2D/3D Graphics Accelerator

- High Performance Real256? Technology 3D Graphic Engine

- Built-in 2 Pixel Rendering Pipelines and 4 Texture Units

- Ultra-AGP? Technology Delivering 2GB/s Bandwidth

- Advanced HW Acceleration for DVD Playback

- Shared Memory up to 128MB

- Fully DirectX7 Compliant Graphics Engine

- Built-in High Performance VLIM T/L Engine

NTSC/PAL TV or Secondary CRT Monitor or Digital LCD Monitor

- Support SiS301B Video Bridge for Dual Display

- LVDS/TMDS Transmitter Interface

MuTIOL? Delivering 533MB/s Bandwidth

- Proprietary Interconnect between SiS740 and SiS961

- Bi-Directional 16-bit Data Bus at 266MHz Operating Frequency

SiS961 MuTIOL? Media I/O

MuTIOL? Delivering 533MB/s Bandwidth

- Proprietary Interconnect between SiS740 and SiS961

- Bi-Directional 16-bit Data Bus at 266MHz Operating Frequency

Integrated Fast Ethernet/Home Networking Controller with MII Interface

- Support 10/100Mb Fast Ethernet or 1/10Mb HomePNA2.0 with external PHY

- Compliant with ACR and CNR slots

Integrated Audio/Modem Controllers with AC'97 Interface

- Support AC'97 V2.2 Audio Codec and Modem Codec

- Support 5.1 Channel Speakers

Advanced Power Management - ACPI 1.1 and APM 1.2 Compliant Dual USB OpenHCI Host Controllers with 6 USB Ports

Dual IDE Channels with ATA 100/66/33

Support Up to 6 PCI Masters

LPC 1.0 Interface

Integrated RTC

Integrated Keyboard/PS2 Mouse Controller

PC2001 Compliant

SiS740 chipset overview

SiS740 Integrated DDR Solution for AMD? Platform

SiS 740 IGUI HMC

The SiS 740 IGUI Host & Memory Controller integrates a high performance and high quality 3D/2D Graphical Accelerator, Video Accelerator and Motion Compensation MPEG1/MPRII Video Decoder for the AMD Socket A series based PC systems. It also integrates a high performance 2.1GB/s DDR-266 Memory controller to sustain the bandwidth demand form the integrated GUI, host processor, as well as the multi I/O masters. A wide bandwidth and high throughput MuTIOL Connect is incorporated to interconnect the SiS 740 to a series 961 MuTIOL Media I/O.

The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture and Geometry Transform/lighting engines, and a 128 bit 2D accelerator with 1T pipeline BITBLT engine. It also features a Video high quality DVD playback. A 12 bit DDR digital video link interfaced to SiS 301 package in 100-pin PQFP is incorporated to expand the SiS 740 functionality in support of the secondary display, in addition to the default primary CRT display. The SiS 301 Video Bridge integrates an NTSL/PAL video encoder with Macro Vision Ver. 7.1.L1 option for TV display, A TMDS transmitter with Bi-linear scaling capability for TFT LCD panel support, and an analog RGB port to support a secondary CRT. The primary CRT display and the extended secondary display (TV, TFT LCD Panel, 2?|nd CRT) features the Dual View capability in the sense that both can generate the display in independent resolutions, color depths, and frame rates.

The SiS 740 Host Interface features the S2K complaint bus driver technology to support AMD Polamino, Athlon, and Duron processors. It also supports the AMD PowerNow! TM dynamic power management technique. A Unified Memory Controller supporting SDR-133 or DDR-266 Dram is incorporated, delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphical accelerator, or the I/O bus masters. The memory controller also supports the Suspend-to-RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source delivers power. The SiS 740 adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 128MB.

Two separate buses, Host-t-GUI in the width of 64 bits, and GUI-t-Memory Controller in the width of 128 bit are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In SDR-133, or DDR-266 memory subsystem, the 128 bit GUI-t-MC bus will attain the AGP4X or AGP8X equivalent texture transfer rate, respectively. The Integrated Memory Controller mainly comprises the Memory Arbiter, the M-data/M-CoMmanD Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI, Host Controller, and I/O bus masters based on a default optimi zed priority list with the capability of dynamically prioritizing the I/O bus master requests in a bit to offering privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the max. tolerate period of 10us. Prior to the memory access request pushed into the M-data queue, any command complaint to the paging mechanism is generated and pushed into the M-CMD queue. The M-Data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling command requests in the background when the data requests streamlines in the foreground.