SiS746
( North Bridge Chipset )
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First AGP8X-supporting Chipset for
AMD Platform
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The SiS746 Host & Memory & AGP Controller integrates a high performance
host interface for AMD Socket A processor, a high performance memory
controller, a AGP interface, and SiS MuTIOL™ Technology connecting with
SiS963 MuTIO™L Media IO. The SiS746 Host Interface features the S2K
complaint bus driver technology to support AMD Polamino, Morgan, Athlon/XP,
and Duron processors. It also supports the AMD PowerNow!™ dynamic power
management technique. The Memory Controller can support DDR and offer
bandwidth up to 2.7GB/s under DDR333 in order to sustain the bandwidth
demand from host processor, as well as the multi I/O masters and AGP
masters. The memory controller also supports the Suspend-to-RAM function
by retaining the CKE# pins asserted in ACPI S3 state in which only AUX
source delivers power.
The AGP interface can support external AGP slot with AGP 2X/4X/8X
capability and Fast Write Transactions. A high bandwidth and mature SiS
MuTIOL™ technology is incorporated to connect SiS746 and SiS963 MuTIOL™
Media IO together. SiS MuTIOL™ technology is developed into three
layers, the Multi-Threaded I/O Link Layer delivering 1.2 GB/s bandwidth
to connect embedded DMA Master devices and external PCI masters to
interface to Multi-Threaded I/O Link Layer, the Multi-Threaded I/O Link
Encoder/Decoder in SiS963 to transfer data w/ 1GB/s bandwidth from/to
Multi-Threaded I/O Link Layer to/from SiS746, and the Multi-Threaded I/O
Link Encoder/Decoder in SiS746 to transfer data w/ 1GB/s from/to memory
sub-system to/from the Multi-Threaded I/O Link Encoder/Decoder in
SiS963.
PC2001 Compliance
High Performance Host Interface
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Supports AMD Socket A CPU: Polamino, Morgan,
AthlonXP, & Duron |
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Synchronous/Asynchronous Host-t-DRAM Timing:
100/200, 133/200, 100/266, 133/266, 100/333, 133/333 |
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S2K compliant bus driver with auto
compensation capability |
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Supports AMD PowerNow!™ dynamic power
management function |
64 bit high performance DDR-266/333 Memory
Controller
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Supports 200/266/333 DDR SDRAM |
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3 Unbuffered DIMM of 2.5 volt DDR SDRAM |
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Supports up to 2 unbuffered DIMM DDR333 or
up to 3 unbuffered double-sided DIMM DDR266/200 |
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Up to 1 GB per DIMM with max. memory size up
to 3 GB |
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Supports 16Mb, 64Mb, 128Mb, 256Mb, 512Mb
SDRAM technology with page size from 2KB up to 16KB |
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Sustains DDR SDRAM CAS Latency at options of
2, 2.5, & 3 clocks |
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Programmable buffer strength optimizing
performance and stability |
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Suspend to DRAM state |
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High performance unified memory controller
optimizing the DRAM bus utilization |
Integrated A.G.P. Compliant Target/66MHz
Host-to-PCI Bridge
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AGP v3.0 Compliant |
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Support AGP 8X/4X/2X Interface |
High throughout MuTIOL™ Connect interfaced to
SiS963 MuTIOL™ Media I/O
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Bi-directional 16 bit data bus |
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1 GB/s performance in 133MHz x 4 mode |
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Distributed arbitration strategy with
enhanced mode of contiguous DMA data streaming |
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Packet based, pipelining, and split
transaction scheme |
Dedicated Isochronous Response Queue
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Serves Isochronous downstream transfers
responsive to the memory read requests originated from USB or
audio/modem controllers |
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Offers privilege service to guarantee
minimum latency & timely delivery |
NAND Tree for Ball Connectivity Testing
713-Balls BGA Package
1.8V Core with Mixed 0.9V ~ 1.9V, 2.5V IO
CMOS Technology
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