Product overview

SiS305 is one of the chips of the SiS 128-bit graphics accelerator family. With a 365-pin PBGA package, SiS305 integrates a 2X AGP controller with full side-band support, a 128-bit 3D/2D graphics engine and a motion compensation accelerator. It offers a complete 64/32-bit memory data bus. Embedded with a 128-bit 2D engine, it can achieve ultra high 2D performance with the maximum memory bandwidth up to 1 GB/s. An optimized 3D pipeline architecture is implemented for eliminating the overhead resulting from texture read, Z-buffer read/write and destination read latencies and achieving a sustain throughput of over 90% of peak throughput even when texture, Z buffer and alpha blending functions are all enabled. SiS305 also includes a video accelerator and a high performance DVD motion compensation logic to provide very smooth DVD playback. SiS305 provides a 24-bit digital interface to support a secondary display, which is independent of primary CRT display.

SiS301 Product overview

There is a video bridge which is an accompany chip of SiS305 (support TV function only)

- A NTSC video encoder with Macro Vision Ver. 7.01L1 option for TV display

- A PAL video encoder with Macro Vision Ver. 7.01L1 option for TV display

- The package type is 100-pin TQFP.