VIA Cyrix MII Processor

A smart PC buy means getting the best performance for an affordable price. That's the value you'll get with a computer featuring the VIA Cyrix® MII™ processor!

The VIA Cyrix® MII™ processor delivers all the performance you need to handle all your computing and communications needs -- from surfing the Internet and playing the most exciting new games to running all a full range of productivity applications in the home or the office.

Available at speeds of up to PR433, the VIA Cyrix® MII™ processor's powerful design enhancements increase bandwidth and improve performance. And with MMX™ enhanced technology, the VIA Cyrix® MII™ processor brings your multimedia applications to life with brilliant images and crystal clear sound.

Fully compatible with Windows® 95 and 98, the VIA Cyrix® MII™ delivers proven technology for reliable, quality computing you can count on. Whether you're buying a PC for the office or your first home PC or Internet Appliance, the VIA Cyrix® MII™ processor makes it a smart buy - premium performance at an affordable price.

VIA Cyrix®MII®Processor Brief

nhanced Seventh-Generation Architecture
- VIA Cyrix®MII®- PR300 - PR433
- 64K 4-Way Unified Write-Back Cache
- 2 Level TLB (16 Entry L1, 384 Entry L2)
- Branch Prediction with a 512-entry BTB
- Enhanced Memory Management Unit
- Scratchpad RAM in Unified Cache
- Optimized for both 16- and 32-Bit Code
- High Performance 80-Bit FPU

X86 Instruction Set Includes MMX®Instructions
- Compatible with MMX®Technology
- Runs Windows®95, Windows®98, Windows®3.x,   Windows® NT, DOS, Linux, UNIX® OS/2® Solaris ®   and other leading operating systems

Other Features
- Socket 7 Compatible - 2.9 V Core and 2.2 V Core, 3.3 V   I/O
- Flexible Core/Bus Clock Ratios (2x, 2.5x, 3x, 3.5x)
- Leverages Existing Socket Infrastructure

Architecture Overview
The VIA Cyrix®MII®processor is based on the proven 6x86 core and is superscalar in that it contains two separate pipelines that allow multiple instructions to be processed at the same time. The use of advanced processing technology and superpipelining (increased number of pipeline stages) allow the VIA Cyrix®MII®processor to achieve high clocks rates. Through the use of unique architectural features, the VIA Cyrix®MII®processor eliminates many data dependencies and resource conflicts, resulting in optimal performance for both 16-bit and 32-bit x86 software. For maximum performance, the VIA Cyrix® MII®processor contains two caches, a large unified 64 Kbyte 4-way set associative write-back cache and a small high speed instruction line cache. To provide support for multimedia operations, the cache can be turned into a scratchpad RAM memory on a line by line basis. The cache area set aside as scratchpad memory acts as a private memory for the CPU and does not participate in cache operations. Within the VIA Cyrix®MII®processor there are two TLBs, the main L1 TLB and the larger L2 TLB. The direct-mapped L1 TLB has 16 entries and the 6-way associative L2 TLB has 384 entries. The on-chip FPU has been enhanced to process MMX®instructions as well as the floating point instructions. Both types of instructions execute in parallel with integer instruction processing. To facilitate FPU operations, the FPU features a 64-bit data interface, a four-deep instruction queue and a six-deep store queue.

The processor operates using a split rail power design. The core runs on a 2.9 or 2.2 volt power supply, to minimize power consumption. External signal level compatibility is maintained by using a 3.3 volt power supply for the I/O interface. For mobile systems and other power sensitive applications, the VIA Cyrix®MII®processor incorporates low power suspend mode, stop clock capability, and system management mode (SMM).

Functional Blocks
The VIA Cyrix®MII®processor consists of four major functional blocks:

• Memory Management Unit
• CPU Core
• Cache Unit
• Bus Interface Unit

The CPU contains the superpipelined integer unit, the BTB (Branch Target Buffer) unit and the FPU (Floating Point Unit). The BIU (Bus Interface Unit) provides the interface between the external system board and the processor's internal execution units. During a memory cycle, a memory location is selected through the address lines (A31-A3 and BE7# -BE0#). Data is passed from or to memory through the data lines (D63-D0). Each instruction is read into 256-Byte Instruc-tion Line Cache. The Cache Unit stores the most recently used data and instructions to allow fast access to the information by the Integer Unit and FPU. The CPU core requests instructions from the Cache Unit. The received integer instructions are decoded by either the X or Y processing pipelines within the superpipelined integer unit. If the instruction is a MMX or FPU instruction it is passed to the floating point unit for processing. As required data is fetched from the 64-Kbyte unified cache. If the data is not in the cache it is accessed via the bus interface unit from main memory. The Memory Management Unit calculates physical addresses including addresses based on paging. Physical addresses are calculated by the Memory Management Unit and passed to the Cache Unit and the Bus Interface Unit (BIU).